On the AER Convolution Processors for FPGA
| Autor: | F. Gomez-Rodriguez, R. Paz-Vicente, Anton Civit, Gabriel Jiménez, Alejandro Linares-Barranco, A. Jimenez, M. Rivas |
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| Přispěvatelé: | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores, Universidad de Sevilla. TEP-108: Robótica y Tecnología de Computadores Aplicada a la Rehabilitación |
| Rok vydání: | 2010 |
| Předmět: | |
| Zdroj: | idUS. Depósito de Investigación de la Universidad de Sevilla instname ISCAS |
| Popis: | Image convolution operations in digital computer systems are usually very expensive operations in terms of resource consumption (processor resources and processing time) for an efficient Real-Time application. In these scenarios the visual information is divided into frames and each one has to be completely processed before the next frame arrives in order to warranty the real-time. A spike-based philosophy for computing convolutions based on the neuro-inspired Address-Event- Representation (AER) is achieving high performances. In this paper we present two FPGA implementations of AER-based convolution processors for relatively small Xilinx FPGAs (Spartan-II 200 and Spartan-3 400), which process 64x64 images with 11x11 convolution kernels. The maximum equivalent operation rate that can be reached is 163.51 MOPS for 11x11 kernels, in a Xilinx Spartan 3 400 FPGA with a 50MHz clock. Formulations, hardware architecture, operation examples and performance comparison with frame-based convolution processors are presented and discussed. Ministerio de Ciencia e Innovación TEC2006-11730-C03-02 Ministerio de Ciencia e Innovación TEC2009-10639-C04-02 Junta de Andalucía P06-TIC-01417 |
| Databáze: | OpenAIRE |
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