SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping
| Autor: | David Trilla, Sergi Alcaide, Jaume Abella, Oriol Sala, Francisco Bas, Fabio Mazzocchetti, Ruben Lorenzo, Guillem Cabo, Guillermo Gil |
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| Přispěvatelé: | Universitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors, Barcelona Supercomputing Center |
| Rok vydání: | 2021 |
| Předmět: |
Flexibility (engineering)
Multi-core processor Computer science business.industry Aerospace electronics Multiprocessadors Seguretat informàtica Lockstep Thread (computing) Avionics Multicore processing Redundancy Hardware Software Computer security Task analysis Redundancy (engineering) Multiprocessors Safety business Field-programmable gate array Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC] Computer hardware |
| Zdroj: | IOLTS 2021 IEEE 27th International Symposium on Testing and Robust System Design (IOLTS) UPCommons. Portal del coneixement obert de la UPC Universitat Politècnica de Catalunya (UPC) |
| DOI: | 10.1109/iolts52814.2021.9486715 |
| Popis: | Safety-related systems, such as those in automotive, avionics and space, impose the existence of appropriate safety measures to meet the safety requirements of the system. In the case of the highest integrity level functionalities (e.g. ASIL-D in automotive), diverse redundancy must be deployed to avoid unreasonable risk of a single fault leading the system to a failure (e.g. using lockstepped cores). However, existing lockstep solutions are either (1) highly intrusive and inflexible coupling two cores with hardware means, or (2) costly in terms of execution time and monitoring if a software monitor thread checks that cores running redundantly preserve sufficient staggering. This paper presents SafeDE, a Diversity Enforcement hardware module providing light-lockstep support by means of a non-intrusive and flexible hardware module that preserves staggering across cores running redundant threads, thus bringing time diversity. SafeDE reconciles the lightness and flexibility of software-only solutions, even allowing using the cores without any lockstepping, as well as the tighter staggering of hardware-only solutions that allow using staggering values of few cycles, instead of hundreds of microseconds, as for software-only solutions. Our integration of SafeDE in a RISC-V FPGA-based space multicore from Cobham Gaisler shows that staggering is effectively preserved, and SafeDE overheads are negligible in terms of area and performance due to staggering. This work has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement no. 871467. This work has also been partially supported by the Spanish Ministry of Science and Innovation under grant PID2019-107255GB. |
| Databáze: | OpenAIRE |
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