Ring VCO Phase Noise Optimization by Pseudo-Differential Architecture in 28nm FD-SOI CMOS
| Autor: | Yann Deval, Magali De Matos, Andreia Cathelin, David Gaidioz |
|---|---|
| Přispěvatelé: | Equipe, Circuits and Systems |
| Rok vydání: | 2020 |
| Předmět: |
Materials science
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Transistor dBc Biasing 7. Clean energy [SPI.TRON] Engineering Sciences [physics]/Electronics law.invention Voltage-controlled oscillator CMOS law Phase noise Electronic engineering Inverter Figure of merit |
| Zdroj: | ISCAS 2020 IEEE International Symposium on Circuits and Systems (ISCAS) |
| DOI: | 10.1109/iscas45731.2020.9180557 |
| Popis: | This paper presents a Pseudo-differential Ring- VCO (PRVCO) architecture optimized to improve by more than a factor of two the phase noise performance of regular single-ended inverter-based Ring-VCO (RVCO). Two RVCO topologies are compared and integrated in 28nm FD-SOI CMOS technology from STMicroelectronics. Based on a double tuning approach, each oscillator presents a Frequency Tuning Range (FTR) between 0.7 GHz and 2.8 GHz (120 % of FTR). The coarse tuning is realized by the local supply voltage variation, while the fine tuning is obtained via the transistors wide range body biasing specific to FD-SOI. Under typical configuration, the PRVCO presents a phase noise (PN) performance of – 95.7 dBc/Hz at 1 MHz offset frequency, which represents a 4 dB improvement compared to the inverter-based RVCO phase noise at 1.7 GHz. Both fabricated RVCOs performances are compared to the state-of-art regarding their oscillator’s and VCO’s Figure of Merit (FoM). |
| Databáze: | OpenAIRE |
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