Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around
| Autor: | Youssouf Guerfi, Guilhem Larrieu |
|---|---|
| Přispěvatelé: | Équipe Matériaux et Procédés pour la Nanoélectronique (LAAS-MPN), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées |
| Jazyk: | angličtina |
| Předmět: |
Materials science
Nanowire Nanochemistry Nanotechnology Drain-induced barrier lowering 02 engineering and technology 01 natural sciences law.invention Materials Science(all) law 0103 physical sciences Miniaturization General Materials Science [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics 010302 applied physics Nano Express business.industry Transistor 021001 nanoscience & nanotechnology Condensed Matter Physics Subthreshold slope Optoelectronics Inverter Field-effect transistor 0210 nano-technology business |
| Zdroj: | Nanoscale Research Letters Nanoscale Research Letters, 2016, 11, pp.210. ⟨10.1186/s11671-016-1396-7⟩ Nanoscale Research Letters, SpringerOpen, 2016, 11, pp.210. ⟨10.1186/s11671-016-1396-7⟩ |
| ISSN: | 1931-7573 1556-276X |
| DOI: | 10.1186/s11671-016-1396-7 |
| Popis: | International audience; Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires’ suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction channel and then a better immunity against the short channel effects (SCE). In this letter, a large-scale process of GAA vertical silicon nanowire (VNW) MOSFETs is presented. A top-down approach is adopted for the realization of VNWs with an optimum reproducibility followed by thin layer engineering at nanoscale. Good overall electrical performances were obtained, with excellent electrostatic behavior (a subthreshold slope (SS) of 95 mV/dec and a drain induced barrier lowering (DIBL) of 25 mV/V) for a 15-nm gate length. Finally, a first demonstration of dual integration of n-type and p-type VNW transistors for the realization of CMOS inverter is proposed. |
| Databáze: | OpenAIRE |
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