A Matrix–Matrix Multiplication methodology for single/multi-core architectures using SIMD
| Autor: | Angeliki Kritikakou, Vasilios Kelefouras, Costas E. Goutis |
|---|---|
| Rok vydání: | 2014 |
| Předmět: |
Multi-core processor
Speedup Memory hierarchy CPU cache Computer science Cache coloring Parallel computing Cache pollution Cache-oblivious algorithm Theoretical Computer Science Smart Cache Memory management Shared memory Hardware and Architecture Cache invalidation Page cache Cache SIMD Cache algorithms Software Information Systems |
| Zdroj: | The Journal of Supercomputing. 68:1418-1440 |
| ISSN: | 1573-0484 0920-8542 |
| DOI: | 10.1007/s11227-014-1098-9 |
| Popis: | In this paper, a new methodology for speeding up Matrix–Matrix Multiplication\ud using Single Instruction Multiple Data unit, at one and more cores having a\ud shared cache, is presented. This methodology achieves higher execution speed than\ud ATLAS state of the art library (speedup from 1.08 up to 3.5), by decreasing the number\ud of instructions (load/store and arithmetic) and the data cache accesses and misses in\ud thememory hierarchy. This is achieved by fully exploiting the software characteristics\ud (e.g. data reuse) and hardware parameters (e.g. data caches sizes and associativities)\ud as one problem and not separately, giving high quality solutions and a smaller search\ud space. |
| Databáze: | OpenAIRE |
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