Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch

Autor:	Seiji Kajihara, Michael A. Kochte, Xiaoqing Wen, Stefan Holst, K. Asada, Jun Qian, Hans-Joachim Wunderlich, Eric Schneider, Kohei Miyase
Jazyk:	angličtina
Rok vydání:	2016
Předmět:	logic path Computer science Test quality IR-drop Real-time computing test clock stretch false capture failure Logic gate launch switching activity clock path X-filling Power network design Simulation
Zdroj:	ATS
ISSN:	2377-5386
Popis:	IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (Cps). Excessive extra delay along LPs compromises test yields due to false capture failures, while excessive extra delay along CPs compromises test quality due to test clock stretch. This paper is the first to mitigate the impact of LSA on both LPs and CPs with a novel LCPA (Logic/Clock Path-Aware) at-speed scan test generation scheme, featuring (1) a new metric for assessing the risk of false capture failures based on the amount of LSA around both LPs and CPs, (2) a procedure for avoiding false capture failures by reducing LSA around LPs or masking uncertain test responses, and (3) a procedure for reducing test clock stretch by reducing LSA around CPs. Experimental results demonstrate the effectiveness of the LCPA scheme in improving test yields and test quality. 2015 IEEE 24th Asian Test Symposium (ATS), 22-25 November 2015, Mumbai, India
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ab5da88a2b4aa6fe340eab91b25f7e0a https://kyutech.repo.nii.ac.jp/records/6375 Zobrazit plný text záznamu