Speeding up behavioral test pattern generation using an algorithmicimprovement
| Autor: | N. Giambiasi, L. Vandeventer, J.F. Santucci |
|---|---|
| Přispěvatelé: | EERIE, IMT - MINES ALES (IMT - MINES ALES), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT), Sciences pour l'environnement (SPE), Université Pascal Paoli (UPP)-Centre National de la Recherche Scientifique (CNRS), Laboratoire des Sciences de l'Information et des Systèmes (LSIS), Aix Marseille Université (AMU)-Université de Toulon (UTLN)-Arts et Métiers Paristech ENSAM Aix-en-Provence-Centre National de la Recherche Scientifique (CNRS), IEEE, Centre National de la Recherche Scientifique (CNRS)-Université Pascal Paoli (UPP), Centre National de la Recherche Scientifique (CNRS)-Arts et Métiers Paristech ENSAM Aix-en-Provence-Université de Toulon (UTLN)-Aix Marseille Université (AMU) |
| Jazyk: | angličtina |
| Rok vydání: | 1994 |
| Předmět: |
Theoretical computer science
ATPG Computer science Heuristic 020208 electrical & electronic engineering Hardware description language Decision tree 02 engineering and technology Pattern generation Automatic test pattern generation [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation 020202 computer hardware & architecture Test (assessment) IEEE Digital pattern generator Behavioral Testing 0202 electrical engineering electronic engineering information engineering Arithmetic [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Focus (optics) computer computer.programming_language |
| Zdroj: | Proceedings of 12th IEEE VLSI Test Symposium, 1994. 12th IEEE VLSI Test Symposium 12th IEEE VLSI Test Symposium, 1994, Cherry Hill, NJ, United States. pp.226-231, ⟨10.1109/VTEST.1994.292308⟩ VTS |
| DOI: | 10.1109/VTEST.1994.292308⟩ |
| Popis: | webpage : http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?isnumber=7228&arnumber=292308&count=71&index=35; International audience; n this paper, we focus on an improvement of test pattern generation for circuit descriptions written in hardware description languages according to their behavior. The improvement method stems from the “headlines” defined at the gate level by structural test approaches. The improvement method is implemented and inserted in a behavioral test pattern generator in order to be validated. Experimental results have been obtained which show the efficiency of our approach |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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