Micro-architectural analysis of in-memory OLTP: Revisited
| Autor: | Ahmad Yasin, Anastasia Ailamaki, Utku Sirin, Pinar Tözün, Danica Porobic |
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| Rok vydání: | 2021 |
| Předmět: |
010302 applied physics
Hardware_MEMORYSTRUCTURES Exploit Computer science Process (computing) 02 engineering and technology computer.software_genre Data structure 01 natural sciences Reduction (complexity) Concurrency control Hardware and Architecture 020204 information systems 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Operating system Online transaction processing Cache Central processing unit computer Information Systems |
| Zdroj: | The VLDB Journal, Volume 30 Sirin, U, Tözün, P, Porobic, D, Yasin, A & Ailamaki, A 2021, ' Micro-architectural analysis of in-memory OLTP: Revisited ', The VLDB Journal, vol. 30, no. 4, pp. 641-665 . https://doi.org/10.1007/s00778-021-00663-8 |
| ISSN: | 0949-877X 1066-8888 |
| DOI: | 10.1007/s00778-021-00663-8 |
| Popis: | Micro-architectural behavior of traditional disk-based online transaction processing (OLTP) systems has been investigated extensively over the past couple of decades. Results show that traditional OLTP systems mostly under-utilize the available micro-architectural resources. In-memory OLTP systems, on the other hand, process all the data in main-memory and, therefore, can omit the buffer pool. Furthermore, they usually adopt more lightweight concurrency control mechanisms, cache-conscious data structures, and cleaner codebases since they are usually designed from scratch. Hence, we expect significant differences in micro-architectural behavior when running OLTP on platforms optimized for in-memory processing as opposed to disk-based database systems. In particular, we expect that in-memory systems exploit micro-architectural features such as instruction and data caches significantly better than disk-based systems. This paper sheds light on the micro-architectural behavior of in-memory database systems by analyzing and contrasting it to the behavior of disk-based systems when running OLTP workloads. The results show that, despite all the design changes, in-memory OLTP exhibits very similar micro-architectural behavior to disk-based OLTP: more than half of the execution time goes to memory stalls where instruction cache misses or the long-latency data misses from the last-level cache (LLC) are the dominant factors in the overall execution time. Even though ground-up designed in-memory systems can eliminate the instruction cache misses, the reduction in instruction stalls amplifies the impact of LLC data misses. As a result, only 30% of the CPU cycles are used to retire instructions, and 70% of the CPU cycles are wasted to stalls for both traditional disk-based and new generation in-memory OLTP. |
| Databáze: | OpenAIRE |
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