Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters
| Autor: | Luca Benini, Davide Rossi, Giuseppe Tagliavini, Florian Glaser, Germain Haugou, Qiuting Huang |
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| Přispěvatelé: | Florian Glaser, Giuseppe Tagliavini, Davide Rossi, Germain Haugoug, Qiuting Huang, Luca Benini |
| Jazyk: | angličtina |
| Rok vydání: | 2020 |
| Předmět: |
Power management
Signal Processing (eess.SP) FOS: Computer and information sciences Energy-efficient embedded parallel computing fine-grain parallelism tightly memory-coupled multiprocessors Computer science 020208 electrical & electronic engineering Multiprocessing 02 engineering and technology Parallel computing Synchronization 020202 computer hardware & architecture Computational Theory and Mathematics Kernel (image processing) Hardware and Architecture Signal Processing Hardware Architecture (cs.AR) 0202 electrical engineering electronic engineering information engineering Cluster (physics) FOS: Electrical engineering electronic engineering information engineering Electrical Engineering and Systems Science - Signal Processing Computer Science - Hardware Architecture Efficient energy use |
| Zdroj: | IEEE Transactions on Parallel and Distributed Systems |
| Popis: | The steeply growing performance demands for highly power- and energy-constrained processing systems such as end-nodes of the Internet-of-Things (IoT) have led to parallel near-threshold computing (NTC), joining the energy-efficiency benefits of low-voltage operation with the performance typical of parallel systems. Shared-L1-memory multiprocessor clusters are a promising architecture, delivering performance in the order of GOPS and over 100 GOPS/W of energy-efficiency. However, this level of computational efficiency can only be reached by maximizing the effective utilization of the processing elements (PEs) available in the clusters. Along with this effort, the optimization of PE-to-PE synchronization and communication is a critical factor for performance. In this article, we describe a light-weight hardware-accelerated synchronization and communication unit (SCU) for tightly-coupled clusters of processors. We detail the architecture, which enables fine-grain per-PE power management, and its integration into an eight-core cluster of RISC-V processors. To validate the effectiveness of the proposed solution, we implemented the eight-core cluster in advanced 22 nm FDX technology and evaluated performance and energy-efficiency with tunable microbenchmarks and a set of real-life applications and kernels. The proposed solution allows synchronization-free regions as small as 42 cycles, over 41× smaller than the baseline implementation based on fast test-and-set access to L1 memory when constraining the microbenchmarks to 10 percent synchronization overhead. When evaluated on the real-life DSP-applications, the proposed SCU improves performance by up to 92 and 23 percent on average and energy efficiency by up to 98 and 39 percent on average. |
| Databáze: | OpenAIRE |
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