Enabling Packet Classification with Low Update Latency for SDN Switch on FPGA
| Autor: | Zilin Shi, Chenglong Li, Tao Li, Baosheng Wang, Junnan Li |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
OpenFlow
update latency Computer science lcsh:TJ807-830 Geography Planning and Development lcsh:Renewable energy sources 02 engineering and technology Management Monitoring Policy and Law Bit array 0202 electrical engineering electronic engineering information engineering Latency (engineering) Field-programmable gate array lcsh:Environmental sciences FPGA lcsh:GE1-350 020203 distributed computing Renewable Energy Sustainability and the Environment business.industry lcsh:Environmental effects of industries and plants Packet Classification 020206 networking & telecommunications lcsh:TD194-195 SDN switch Bit-Vector business Packet classification Computer hardware FPGA prototype |
| Zdroj: | Sustainability Volume 12 Issue 8 Sustainability, Vol 12, Iss 3068, p 3068 (2020) |
| ISSN: | 2071-1050 |
| DOI: | 10.3390/su12083068 |
| Popis: | Field Programmable Gate Array (FPGA) is widely used in real-time network processing such as Software-Defined Networking (SDN) switch due to high performance and programmability. Bit-Vector (BV)-based approaches can implement high-performance multi-field packet classification, on FPGA, which is the core function of the SDN switch. However, the SDN switch requires not only high performance but also low update latency to avoid controller failure. Unfortunately, the update latency of BV-based approaches is inversely proportional to the number of rules, which means can hardly support the SDN switch effectively. It is reasonable to split the ruleset into sub-rulesets that can be performed in parallel, thereby reducing update latency. We thus present SplitBV for the efficient update by using several distinguishable exact-bits to split the ruleset. SplitBV consists of a constrained recursive algorithm for selecting the bit positions that can minimize the latency and a hybrid lookup pipeline. It can achieve a significant reduction in update latency with negligible memory growth and comparable high performance. We implement SplitBV and evaluate its performance by simulation and FPGA prototype. Experimental results show that our approach can reduce 73% and 36% update latency on average for synthetic 5-tuple rules and OpenFlow rules respectively. |
| Databáze: | OpenAIRE |
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