Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST
| Autor: | Daniele Rossi, C. Tirumurti, Filippo Fuzzi, Martin Omana, Cecilia Metra, Rajesh Galivanche |
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| Přispěvatelé: | Omaña, Martin, Rossi, Daniele, Fuzzi, Filippo, Metra, Cecilia, Tirumurti, Chandrasekharan Chandra, Galivanche, Rajesh |
| Rok vydání: | 2017 |
| Předmět: |
Computer science
Test compression 02 engineering and technology Automatic test pattern generation 01 natural sciences Reduction (complexity) test 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Logic BIST (LBIST) microprocessor power droop (PD) test Overhead (computing) Voltage droop Electrical and Electronic Engineering 010302 applied physics Sequential logic business.industry 020202 computer hardware & architecture Logic BIST (LBIST) Built-in self-test power droop (PD) Hardware and Architecture Embedded system Fault coverage microprocessor business Software |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:238-246 |
| ISSN: | 1557-9999 1063-8210 |
| Popis: | The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails and increase in yield loss. In this paper, we propose a novel scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based LBIST using the launch-on-capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the LBIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve a target fault coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared with recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC. |
| Databáze: | OpenAIRE |
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