Innovative Low-Power Self-Nanoconfined Phase-Change Memory
| Autor: | Gauthier Lefevre, C. Sabbione, Sylvain David, Etienne Nowak, J. Garrione, N. Castellani, Marie-Claire Cyrille, Anna Lisa Serra, Nicolas Bernier, Christophe Vallée, Guillaume Bourgeois, Gabriele Navarro, Mathieu Bernard, O. Cueto, Christelle Charpin-Nicolle |
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| Přispěvatelé: | CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information, Laboratoire des technologies de la microélectronique (LTM ), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), European Project: 783176,WAKeMeUp |
| Jazyk: | angličtina |
| Rok vydání: | 2021 |
| Předmět: |
010302 applied physics
business.industry GeSbTe Thermal confinement 01 natural sciences Electronic Optical and Magnetic Materials Power (physics) Phase-change memory chemistry.chemical_compound [SPI]Engineering Sciences [physics] Low power Phase-Change Memory Stack (abstract data type) chemistry 0103 physical sciences Thermal Optoelectronics Electro-thermal simulations Electrical and Electronic Engineering business Current density Scaling Lithography |
| Zdroj: | IEEE Transactions on Electron Devices IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2021, 68 (2), pp.535-540. ⟨10.1109/TED.2020.3044267⟩ IEEE Transactions on Electron Devices, 2021, 68 (2), pp.535-540. ⟨10.1109/TED.2020.3044267⟩ |
| ISSN: | 0018-9383 |
| Popis: | International audience; In this paper, we demonstrate at array level and in industrial like devices, the extreme scaling down to nanometric dimensions of the Phase-Change Memory technology thanks to an innovative Self-Nano-Confined PCM device (SNC PCM). We show how such solution based on an optimized GeN/GeSbTe stack enables programming down to 50 $\mu$A and endurance up to more than 10$^8$ cycles in 4 kb arrays, with the huge advantage of having no dependency on the critical lithography dimension used. We further demonstrate that the high thermal confinement achieved in such extremely confined PCM makes the engineering of the SET pulse becoming fundamental in order to assure a reduced SET resistance drift. Moreover, thanks to physico-chemical analyses and 3D TCAD electro-thermal simulations we demonstrate the Self-Nano-Confined phenomenon, revealing an effective scaling of the PCM down to around 12 nm and how it improves the thermal efficiency of the device thanks to a reduced current density and thermal stress in the system. |
| Databáze: | OpenAIRE |
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