Experimental and theoretical understanding of Forming, SET and RESET operations in Conductive Bridge RAM (CBRAM) for memory stack optimization
| Autor: | J. Guy, G. Molas, A. Roule, O. Cueto, S. Barraud, G. Le Carval, J. Cluzel, O. Pollet, Mathieu Bernard, Veronique Sousa, H. Grampeix, L. Perniola, B. De Salvo, Gerard Ghibaudo, Alain Toffoli, C. Carabasse, P. Blaise, Fabien Clermidy, Vincent Delaye, P. Brianceau, V. Balan |
|---|---|
| Přispěvatelé: | Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS) |
| Jazyk: | angličtina |
| Rok vydání: | 2014 |
| Předmět: |
Stack-based memory allocation
Engineering Voltage reduction Programmable metallization cell business.industry Electrical engineering Set (abstract data type) Stack (abstract data type) Electronic engineering Kinetic Monte Carlo [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics business Reset (computing) Voltage |
| Zdroj: | 2015 IEDM Technical Digest 2014 IEEE International Electron Devices Meeting (IEDM) 2014 IEEE International Electron Devices Meeting (IEDM), Dec 2014, San Francisco, United States. pp.6.5.1-6.5.4, ⟨10.1109/IEDM.2014.7046997⟩ |
| DOI: | 10.1109/IEDM.2014.7046997⟩ |
| Popis: | International audience; In this paper, we deeply investigate for the 1st time at our knowledge the impact of the CBRAM memory stack on the Forming, SET and RESET operations. Kinetic Monte Carlo simulations, based on inputs from ab-initio calculations and taking into account ionic hopping and chemical reaction dynamics are used to analyse experimental results obtained on decananometric devices. We propose guidelines to optimize the CBRAM stack, targeting Forming voltage reduction, improved trade-off between SET speed and disturb immunity (time voltage dilemma) and window margin increase (RESET efficiency). |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|