Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis
| Autor: | Philippe Coussy, Hannah Badier, Guy Gogniat, Jean-Christophe Le Lann, Christian Pilato |
|---|---|
| Přispěvatelé: | Equipe Hardware ARchitectures and CAD tools (Lab-STICC_ARCAD), Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC), École Nationale d'Ingénieurs de Brest (ENIB)-Université de Bretagne Sud (UBS)-Université de Brest (UBO)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne)-Institut Mines-Télécom [Paris] (IMT)-Centre National de la Recherche Scientifique (CNRS)-Université Bretagne Loire (UBL)-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-École Nationale d'Ingénieurs de Brest (ENIB)-Université de Bretagne Sud (UBS)-Université de Brest (UBO)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne)-Institut Mines-Télécom [Paris] (IMT)-Centre National de la Recherche Scientifique (CNRS)-Université Bretagne Loire (UBL)-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT), École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne), Politechnico de Milano, Université de Bretagne Sud (UBS), Le Lann, Jean-Christophe |
| Jazyk: | angličtina |
| Rok vydání: | 2021 |
| Předmět: |
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
[INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR] business.industry Computer science Supply chain 020208 electrical & electronic engineering Process (computing) 02 engineering and technology 020202 computer hardware & architecture Core (game theory) Resource (project management) Embedded system High-level synthesis 0202 electrical engineering electronic engineering information engineering Code (cryptography) business Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION Hardware_LOGICDESIGN |
| Zdroj: | DATE'21 Design Automation and Test in Europe DATE'21 Design Automation and Test in Europe, Feb 2021, Grenoble (virtuel), France DATE HAL |
| Popis: | International audience; The increasing design and manufacturing costs are leading to globalize the semiconductor supply chain. However, a malicious attacker can resell a stolen Intellectual Property (IP) core, demanding methods to identify a relationship between a given IP and a potentially fraudulent copy. We propose a method to protect IP cores created with highlevel synthesis (HLS): our method inserts a discrete birthmark in the HLS-generated designs that uses only intrinsic characteristics of the final RTL. The core of our process leverages the side effects of HLS due to specific source-code manipulations, although the method is HLS-tool agnostic. We propose two independent validation metrics, showing that our solution introduces minimal resource and delay overheads (< 6% and < 2%, respectively) and the accuracy in detecting illegal copies is above 96%. |
| Databáze: | OpenAIRE |
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