| Autor: |
Manuel Baumgartner, N. Jossart, Johan Swerts, S. Van Beek, D. Crotti, Eva Grimaldi, Pietro Gambardella, Gouri Sankar Kar, Shreya Kundu, F. Yasin, Laurent Souriau, Kevin Garello, Sebastien Couet, Diana Tsvetanova, Enlong Liu, A. Fumemont, W. Kim, Kristof Croes, Siddharth Rao |
| Přispěvatelé: |
IMEC (IMEC), Catholic University of Leuven - Katholieke Universiteit Leuven (KU Leuven), Eidgenössische Technische Hochschule - Swiss Federal Institute of Technology [Zürich] (ETH Zürich) |
| Rok vydání: |
2018 |
| Předmět: |
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| Zdroj: |
VLSI Circuits
2018 IEEE Symposium on VLSI Circuits
2018 IEEE Symposium on VLSI Circuits, Jun 2018, Honolulu, United States. pp.81-82, ⟨10.1109/VLSIC.2018.8502269⟩
Proceedings of the 2018 IEEE Symposium on VLSI Circuits |
| DOI: |
10.48550/arxiv.1810.10356 |
| Popis: |
We demonstrate for the first time full-scale integration of top-pinned perpendicular MTJ on 300 mm wafer using CMOS-compatible processes for spin-orbit torque (SOT)-MRAM architectures. We show that 62 nm devices with a W-based SOT underlayer have very large endurance (> 5x10^10), sub-ns switching time of 210 ps, and operate with power as low as 300 pJ.
presented at VLSI2018 session C8-2 |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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