From IC Layout to Die Photograph: A CNN-Based Data-Driven Approach
| Autor: | Shao-Yun Fang, Hao-Chiang Shao, Pin-Yian Tsai, Jun-Rei Wu, Chia-Wen Lin, Yan-Hsiu Liu, Chao-Yi Peng |
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| Rok vydání: | 2021 |
| Předmět: |
FOS: Computer and information sciences
Computer science Semiconductor device fabrication Computer Vision and Pattern Recognition (cs.CV) Image and Video Processing (eess.IV) Computer Science - Computer Vision and Pattern Recognition 02 engineering and technology Electrical Engineering and Systems Science - Image and Video Processing Computer Graphics and Computer-Aided Design Integrated circuit layout Die (integrated circuit) 020202 computer hardware & architecture Wafer fabrication Optical proximity correction FOS: Electrical engineering electronic engineering information engineering Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Wafer Electrical and Electronic Engineering Photomask Lithography Algorithm Software |
| Zdroj: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 40:957-970 |
| ISSN: | 1937-4151 0278-0070 |
| DOI: | 10.1109/tcad.2020.3015469 |
| Popis: | We propose a deep learning-based data-driven framework consisting of two convolutional neural networks: i) LithoNet that predicts the shape deformations on a circuit due to IC fabrication, and ii) OPCNet that suggests IC layout corrections to compensate for such shape deformations. By learning the shape correspondences between pairs of layout design patterns and their scanning electron microscope (SEM) images of the product wafer thereof, given an IC layout pattern, LithoNet can mimic the fabrication process to predict its fabricated circuit shape. Furthermore, LithoNet can take the wafer fabrication parameters as a latent vector to model the parametric product variations that can be inspected on SEM images. Besides, traditional optical proximity correction (OPC) methods used to suggest a correction on a lithographic photomask is computationally expensive. Our proposed OPCNet mimics the OPC procedure and efficiently generates a corrected photomask by collaborating with LithoNet to examine if the shape of a fabricated circuit optimally matches its original layout design. As a result, the proposed LithoNet-OPCNet framework can not only predict the shape of a fabricated IC from its layout pattern, but also suggests a layout correction according to the consistency between the predicted shape and the given layout. Experimental results with several benchmark layout patterns demonstrate the effectiveness of the proposed method. 14 pages, 16 figures |
| Databáze: | OpenAIRE |
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