Longevity Framework: Leveraging Online Integrated Aging-Aware Hierarchical Mapping and VF-Selection for Lifetime Reliability Optimization in Manycore Processors
| Autor: | Vijeta Rathore, Thambipillai Srikanthan, Amit Kumar Singh, Vivek Chaturvedi, Muhammad Shafique |
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| Přispěvatelé: | School of Computer Science and Engineering |
| Rok vydání: | 2021 |
| Předmět: |
Aging
Computer science business.industry 02 engineering and technology Chip Lifetime Reliability 020202 computer hardware & architecture Theoretical Computer Science Parsec Manycore processor Process variation Computational Theory and Mathematics Hardware and Architecture Embedded system Scalability 0202 electrical engineering electronic engineering information engineering Benchmark (computing) Computer science and engineering [Engineering] business Software Reliability (statistics) Abstraction (linguistics) |
| Zdroj: | IEEE Transactions on Computers. 70:1106-1119 |
| ISSN: | 2326-3814 0018-9340 |
| DOI: | 10.1109/tc.2020.3006571 |
| Popis: | Rapid device aging in the nano era threatens system lifetime reliability, posing a major intrinsic threat to system functionality. Traditional techniques to overcome the aging-induced device slowdown, such as guardbanding are static and incur performance, power, and area penalties. In a manycore processor, the system-level design abstraction offers dynamic opportunities through the control of task-to-core mappings and per-core operation frequency towards more balanced core aging profile across the chip, optimizing the system lifetime reliability while meeting the application performance requirements. This article presents Longevity Framework (LF) that leverages online integrated aging-aware hierarchical mapping and voltage frequency (VF)-selection for lifetime reliability optimization in manycore processors. The mapping exploration is hierarchical to achieve scalability. The VF-selection builds on the trade-offs involved between power, performance, and aging as the VF is scaled while leveraging the per-core DVFS capabilities. The methodology takes the chip-wide process variation into account. Extensive experimentation, comparing the proposed approach with two state-of-the-art methods, for 64-core and 256-core systems running applications from PARSEC and SPLASH-2 benchmark suites, show an improvement of up to 3.2 years in the system lifetime reliability and 4×improvement in the average core health. The coauthor Dr. Shafique’s contributions in this work was supported in parts by the German Research Foundation (DFG) as part of the GetSURE Project in the scope of SPP1500 priority program “Dependable Embedded Systems”. |
| Databáze: | OpenAIRE |
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