Time-redundancy transformations for adaptive fault-tolerant circuits
| Autor: | Pascal Fradet, Dmitry Burlyaev, Alain Girault |
|---|---|
| Přispěvatelé: | Sound Programming of Adaptive Dependable Embedded Systems (SPADES), Inria Grenoble - Rhône-Alpes, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-Laboratoire d'Informatique de Grenoble (LIG), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre Mendès France - Grenoble 2 (UPMF)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre Mendès France - Grenoble 2 (UPMF)-Université Joseph Fourier - Grenoble 1 (UJF), Université Pierre Mendès France - Grenoble 2 (UPMF)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre Mendès France - Grenoble 2 (UPMF)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS) |
| Jazyk: | angličtina |
| Rok vydání: | 2015 |
| Předmět: |
Triple modular redundancy
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR] Computer science Computation 02 engineering and technology Parallel computing Hardware_PERFORMANCEANDRELIABILITY 01 natural sciences Logic redundancy digital circuits 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Redundancy (engineering) Electronic circuit Digital electronics 010308 nuclear & particles physics business.industry Suite Fault tolerance circuit transformation ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.2: Design Aids/B.5.2.0: Automatic synthesis 020202 computer hardware & architecture [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF] Computer engineering time redundancy fault tolerance business ACM: B.: Hardware/B.5: REGISTER-TRANSFER-LEVEL IMPLEMENTATION/B.5.3: Reliability and Testing/B.5.3.2: Redundant design |
| Zdroj: | 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Jun 2015, Montreal, Canada. ⟨10.1109/AHS.2015.7231164⟩ AHS |
| DOI: | 10.1109/AHS.2015.7231164⟩ |
| Popis: | International audience; We present a novel logic-level circuit transformation technique for the automatic insertion of fault-tolerance properties. The transformations, based on time-redundancy, allow dynamic changes of the level of redundancy without interrupting the computation. The proposed concept of dynamic time redundancy permits adaptive circuits whose fault-tolerance properties can be “on-the-fly” traded-off for throughput. The approach is technologically independent and does not require any specific hardware support. Experimental results on the ITC'99 benchmark suite indicate that the benefits of our method grow with the combinational size of the circuit. Dynamic double and triple time redundant transformations generate circuits 1.7 to 2.9 times smaller than full Triple-Modular Redundancy (TMR). This transformation is a good alternative to TMR for logic-intensive safety-critical circuits where low hardware overhead or only temporary fault-tolerance guarantees are needed. |
| Databáze: | OpenAIRE |
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