Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization
Autor: | Yoichi Momiyama, TaiYu Cheng, Jun Nagayama, Jun Chen, Yutaka Masuda, Masanori Hashimoto |
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Jazyk: | angličtina |
Rok vydání: | 2022 |
Předmět: |
Computer science
Applied Mathematics Mode (statistics) activation-aware slack assignment Energy minimization Topology Computer Graphics and Computer-Aided Design mode-wise voltage-scaling Signal Processing downhill simplex method multi-corner multi-mode Electrical and Electronic Engineering Nelder–Mead method Scaling Voltage |
Zdroj: | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. (3):497-508 |
ISSN: | 0916-8508 |
Popis: | Reducing power consumption is a crucial factor making industrial designs, such as mobile SoCs, competitive. Voltage scaling (VS) is the classical yet most effective technique that contributes to quadratic power reduction. A recent design technique called activation-aware slack assignment (ASA) enhances the voltage-scaling by allocating the timing margin of critical paths with a stochastic mean-time-to-failure (MTTF) analysis. Meanwhile, such stochastic treatment of timing errors is accepted in limited application domains, such as image processing. This paper proposes a design optimization methodology that achieves a mode-wise voltage-scalable (MWVS) design guaranteeing no timing errors in each mode operation. This work formulates the MWVS design as an optimization problem that minimizes the overall power consumption considering each mode duration, achievable voltage lowering and accompanied circuit overhead explicitly, and explores the solution space with the downhill simplex algorithm that does not require numerical derivation and frequent objective function evaluations. For obtaining a solution, i.e., a design, in the optimization process, we exploit the multi-corner multi-mode design flow in a commercial tool for performing mode-wise ASA with sets of false paths dedicated to individual modes. We applied the proposed design methodology to RISC-V design. Experimental results show that the proposed methodology saves 13% to 20% more power compared to the conventional VS approach and attains 8% to 15% gain from the conventional single-mode ASA. We also found that cycle-by-cycle fine-grained false path identification reduced leakage power by 31% to 42%. |
Databáze: | OpenAIRE |
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