Embedded System for Biometric Online Signature Verification
| Autor: | Oscar Miguel-Hurtado, Rafael Ramos-Lara, Enrique Canto-Navarro, Mariano Lopez-Garcia |
|---|---|
| Přispěvatelé: | Enginyeria Electrònica, Universitat Rovira i Virgili. |
| Rok vydání: | 2014 |
| Předmět: |
Dynamic time warping
Biometrics business.industry Computer science Signature (logic) Computer Science Applications Digital signature Control and Systems Engineering Handwriting recognition Embedded system Electrical and Electronic Engineering business Signature recognition Computer hardware Information Systems |
| Zdroj: | Ieee Transactions On Industrial Informatics Repositori Institucional de la Universitat Rovira i Virgili Universitat Rovira i virgili (URV) |
| ISSN: | 1941-0050 1551-3203 |
| DOI: | 10.1109/tii.2013.2269031 |
| Popis: | This paper describes the implementation on field-programmable gate arrays (FPGAs) of an embedded system for online signature verification. The recognition algorithm mainly consists of three stages. First, an initial preprocessing is applied on the captured signature, removing noise and normalizing information related to horizontal and vertical positions. Afterwards, a dynamic time warping algorithm is used to align this processed signature with its template previously stored in a database. Finally, a set of features are extracted and passed through a Gaussian Mixture Model, which reveals the degree of similarity between both signatures. The algorithm was tested using a public database of 100 users, obtaining high recognition rates for both genuine and forgery signatures. The implemented system consists of a vector floating-point unit (VFPU), specifically designed for accelerating the floating-point computations involved in this biometric modality. Moreover, the proposed architecture also includes a microprocessor, which interacts with the VFPU, and executes by software the rest of the online signature verification process. The designed system is capable of finishing a complete verification in less than 68 ms with a clock rated at 40 MHz. Experimental results show that the number of clock cycles is accelerated by a factor of ×4.8 and ×11.1, when compared with systems based on ARM Cortex-A8 and when substituting the VFPU by the Floating-Point Unit provided by Xilinx, respectively. |
| Databáze: | OpenAIRE |
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