Transistor Sizing of Energy-Delay-Efficient Circuits
| Autor: | Paul I. Pénzes, Mika Nyström, Alain J. Martin |
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| Rok vydání: | 2005 |
| Předmět: |
Transistor
Energy consumption law.invention Set (abstract data type) Computer Science::Hardware Architecture Computer Science::Emerging Technologies CMOS law Hardware_INTEGRATEDCIRCUITS Electronic engineering Transistor sizing Energy (signal processing) Hardware_LOGICDESIGN Mathematics Electronic circuit Analytic function |
| Zdroj: | Timing Issues in the Specification and Synthesis of Digital Systems |
| Popis: | This paper studies the problem of transistor sizing of CMOS circuits optimized for energy-delay efficiency, i.e., for optimal Etn where E is the energy consumption and t is the delay of the circuit, while n is a fixed positive optimization index that reflects the chosen trade-off between energy and delay.We propose a set of analytical formulas that closely approximate the optimal transistor sizes. We then study an efficient iteration procedure that can further improve the original analytical solution. Based on these results, we introduce a novel transistor sizing algorithm for energy-delay efficiency. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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