Compiler-Assisted Compaction/Restoration of SIMD Instructions
| Autor: | Alberto Ros, Marc Casas, Thibaud Balem, Juan M. Cebrian, Miquel Moreto, Adrian Barredo, Alexandra Jimborean |
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| Přispěvatelé: | Universitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors, Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Barcelona Supercomputing Center, Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions, Facultades, Departamentos, Servicios y Escuelas::Departamentos de la UMU::Ingeniería y Tecnología de Computadores |
| Jazyk: | angličtina |
| Předmět: |
Computer science
Energia -- Consum Parallel computing Density-time performance computer.software_genre SIMD Instruction set Control flow Predication Code generation Tractament vectorial Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC] Out-of-order execution Parallel processing (Electronic computers) Processament en paral·lel (Ordinadors) Vector processing (Computer science) Exascale computing Vector processor Energy consumption Computational Theory and Mathematics Hardware and Architecture LLVM Signal Processing Compiler computer |
| Zdroj: | UPCommons. Portal del coneixement obert de la UPC Universitat Politècnica de Catalunya (UPC) DIGITUM. Depósito Digital Institucional de la Universidad de Murcia instname IEEE Transactions on Parallel and Distributed Systems (TPDS) |
| ISSN: | 1558-2183 2161-9883 1045-9219 |
| DOI: | 10.1109/tpds.2021.3091015 |
| Popis: | Vector processors (e.g., SIMD or GPUs) are ubiquitous in high performance systems. All the supercomputers in the world exploit data-level parallelism (DLP), for example by using single instructions to operate over several data elements. Improving vector processing is therefore key for exascale computing. However, despite its potential, vector code generation and execution have significant challenges. Among these challenges, control flow divergence is one of the main performance limiting factors. Most modern vector instruction sets, including SIMD, rely on predication to support divergence control. Nevertheless, the performance and energy consumption in predicated codes is usually insensitive to the number of active elements in a predicated mask. Since the trend is that vector register size increases, the energy efficiency of exascale computing systems will become sub-optimal. This article proposes a novel approach to improve execution efficiency in predicated vector codes, the Compiler-Assisted Compaction/Restoration (CACR) technique. Baseline CR delays predicated SIMD instructions with inactive elements, compacting active elements from instances of the same instruction of consecutive loop iterations. Compacted elements form an equivalent dense vector instruction. After executing the dense instructions, their results are restored to the original instructions. However, CR has a significant performance and energy penalty when it fails to find active elements, either due to lack of resources when unrolling or because of inter-loop dependencies. In CACR, the compiler analyzes the code looking for key information required to configure CR. Then, it passes this information to the processor via new instructions inserted in the code. This prevents CR from waiting for active elements on scenarios when it would fail to form dense instructions. Simulated results (gem5) show that CACR improves performance by up to 29 percent and reduces dynamic energy by up to 24.2 percent on average, for a a set of applications with predicated execution. The baseline CR only achieves 18.6 percent performance and 14 percent energy improvements for the same configuration and applications. |
| Databáze: | OpenAIRE |
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