Managing contamination delay to improve Timing Speculation architectures
| Autor: | P. Ramesh, Naga Durga Prasad Avirneni, Arun K. Somani |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Overclocking
Delay insertion General Computer Science Contamination delay Exploit Computer science 020208 electrical & electronic engineering Real-time computing Elmore delay 02 engineering and technology Propagation delay PVT variation Timing speculation Timing errors lcsh:QA75.5-76.95 020202 computer hardware & architecture Control theory Path (graph theory) 0202 electrical engineering electronic engineering information engineering Range (statistics) Timing constraints lcsh:Electronic computers. Computer science Performance improvement |
| Zdroj: | PeerJ Computer Science, Vol 2, p e79 (2016) |
| DOI: | 10.7287/peerj.preprints.1412v2 |
| Popis: | Timing Speculation (TS) is a widely known method for realizing better-than-worst-case systems. Aggressive clocking, realizable by TS, enable systems to operate beyond specified safe frequency limits to effectively exploit the data dependent circuit delay. However, the range of aggressive clocking for performance enhancement under TS is restricted by short paths. In this paper, we show that increasing the lengths of short paths of the circuit increases the effectiveness of TS, leading to performance improvement. Also, we propose an algorithm to efficiently add delay buffers to selected short paths while keeping down the area penalty. We present our algorithm results for ISCAS-85 suite and show that it is possible to increase the circuit contamination delay by up to 30% without affecting the propagation delay. We also explore the possibility of increasing short path delays further by relaxing the constraint on propagation delay and analyze the performance impact. |
| Databáze: | OpenAIRE |
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