Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes
| Autor: | Timothy Saxe, Alfio Di Mauro, Frank K. Gurkaynak, Ket Chong Yap, Luca Benini, Mao Wang, Davide Rossi, Pasquale Davide Schiavone |
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| Přispěvatelé: | Schiavone P.D., Rossi D., Di Mauro A., Gurkaynak F.K., Saxe T., Wang M., Yap K.C., Benini L. |
| Jazyk: | angličtina |
| Rok vydání: | 2021 |
| Předmět: |
FOS: Computer and information sciences
Computer science 02 engineering and technology Encryption 7. Clean energy embedded system open source Gate array field-programmable gate array (FPGA) Hardware Architecture (cs.AR) 0202 electrical engineering electronic engineering information engineering System on a chip Electrical and Electronic Engineering Computer Science - Hardware Architecture Field-programmable gate array Edge computing Embedded systems Field Programmable Gate Array (FPGA) Internet of Things (IoT) Microcontroller Open source RISC-V business.industry 020208 electrical & electronic engineering 020202 computer hardware & architecture Hardware and Architecture Interfacing Analytics microcontroller Embedded system business Software |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 29 (4) |
| Popis: | A wide range of Internet of Things (IoT) applications require powerful, energy-efficient, and flexible end nodes to acquire data from multiple sources, process and distill the sensed data through near-sensor data analytics algorithms, and transmit it wirelessly. This work presents Arnold : a 0.5-to-0.8-V, 46.83- $\mu \text{W}$ /MHz, 600-MOPS fully programmable RISC-V microcontroller unit (MCU) fabricated in 22-nm Globalfoundries GF22FDX (GF22FDX) technology, coupled with a state-of-the-art (SoA) microcontroller to an embedded field-programmable gate array (eFPGA). We demonstrate the flexibility of the system-on-chip (SoC) to tackle the challenges of many emerging IoT applications, such as interfacing sensors and accelerators with nonstandard interfaces, performing on-the-fly preprocessing tasks on data streamed from peripherals, and accelerating near-sensor analytics, encryption, and machine learning tasks. A unique feature of the proposed SoC is the exploitation of body-biasing to reduce leakage power of the eFPGA fabric by up to $18\times $ at 0.5 V, achieving SoA state bitstream-retentive sleep power for the eFPGA fabric, as low as $20.5~\mu \text{W}$ . The proposed SoC provides $3.4\times $ better performance and $2.9\times $ better energy efficiency than other fabricated heterogeneous reconfigurable SoCs of the same class. |
| Databáze: | OpenAIRE |
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