Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint
| Autor: | Ying-Lin Zhao, Weisheng Zhao, Yuanqing Cheng, Aida Todri-Sanial, Jianlei Yang |
|---|---|
| Přispěvatelé: | Beihang University (BUAA), Smart Integrated Electronic Systems (SmartIES), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM) |
| Jazyk: | angličtina |
| Rok vydání: | 2018 |
| Předmět: |
Power supply noise (PSN)
Computer science Multiprocessing 02 engineering and technology 01 natural sciences Theoretical Computer Science Scheduling (computing) 0103 physical sciences Thermal 0202 electrical engineering electronic engineering information engineering [INFO.INFO-DL]Computer Science [cs]/Digital Libraries [cs.DL] [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics 010302 applied physics Job shop scheduling business.industry Temperature Solver 020202 computer hardware & architecture Computer Science Applications Power delivery network (PDN) Computational Theory and Mathematics Task scheduling algorithm Hardware and Architecture Homogeneous Embedded system 3D MPSoCs business Software Efficient energy use |
| Zdroj: | Journal of Computer Science and Technology Journal of Computer Science and Technology, Springer Verlag, 2018, 33 (5), pp.966-983. ⟨10.1007/s11390-018-1868-6⟩ |
| ISSN: | 1000-9000 1860-4749 |
| DOI: | 10.1007/s11390-018-1868-6⟩ |
| Popis: | International audience; Thanks to the emerging 3D integration technology, The multiprocessor system on chips (MPSoCs) can now integrate more IP cores on chip with improved energy efficiency. However, several severe challenges also rise up for 3D ICs due to the die-stacking architecture. Among them, power supply noise becomes a big concern. In the paper, we investigate power supply noise (PSN) interactions among different cores and tiers and show that PSN variations largely depend on task assignments. On the other hand, high integration density incurs a severe thermal issue on 3D ICs. In the paper, we propose a novel task scheduling framework considering both the PSN and the thermal issue. It mainly consists of three parts. First, we extract current stimuli of running tasks by analyzing their power traces derived from architecture level simulations. Second, we develop an efficient power delivery network (PDN) solver to evaluate PSN magnitudes efficiently. Third, we propose a heuristic algorithm to solve the formulated task scheduling problem. Compared with the state-of-the-art task assignment algorithm, the proposed method can reduce PSN by 12% on a 2 × 2 × 2 3D MPSoCs and by 14% on a 3 × 3 × 3 3D MPSoCs. The end-to-end task execution time also improves as much as 5.5% and 7.8% respectively due to the suppressed PSN. |
| Databáze: | OpenAIRE |
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