A low-power microcontroller in a 40-nm CMOS using charge recycling
| Autor: | Juan Echeverri, Arnoud van der Wel, Leo Sevat, Hamed Fatemi, Kristof Blutman, Arjun Majumdar, Jose Pineda de Gyvez, Ajay Kapoor, Jacinto Garcia Martinez, Kofi A. A. Makinwa |
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| Přispěvatelé: | Electronic Systems |
| Jazyk: | angličtina |
| Rok vydání: | 2017 |
| Předmět: |
voltage stacking
Stacking 02 engineering and technology Voltage regulator Hardware_PERFORMANCEANDRELIABILITY level shifter Topology law.invention law 0202 electrical engineering electronic engineering information engineering Hardware_INTEGRATEDCIRCUITS Static random-access memory Electrical and Electronic Engineering Physics Hardware_MEMORYSTRUCTURES business.industry 020208 electrical & electronic engineering Electrical engineering Logic level Balanced voltage islands 020202 computer hardware & architecture Capacitor switched capacitor regulators charge recycling CMOS power management business Voltage drop microcontrollers Voltage |
| Zdroj: | IEEE Journal of Solid State Circuits, 52(4) IEEE Journal of Solid-State Circuits, 52(4):7815353, 950-960. Institute of Electrical and Electronics Engineers |
| ISSN: | 0018-9200 |
| Popis: | A 40-nm microcontroller featuring voltage stacked memory and logic is presented. This involved connecting the power domains of the memory and logic in series, such that the ground of one power domain is connected to the positive supply rail of the other. In this paper, an ARM Cortex-M0+ and its peripherals are powered from 0 V to $V_{{\mathrm{DD}}}$ , while its 4-kB ROM and the 16-kB SRAM are powered from $V_{{\mathrm{DD}}}$ to 2 $V_{{\mathrm{DD}}}$ . Since the memory and logic will, in general, draw different supply currents, the midrail $V_{{\mathrm{DD}}}$ is provided by an on-chip switched capacitor voltage regulator (SCVR). To allow a direct comparison of voltage stacking with a conventional single supply, it can be turned off by configuring the SCVR to power both the memory and logic from 0 V and $V_{{\mathrm{DD}}}$ . Turning on voltage stacking results in 96% power conversion efficiency, while the active converter area is reduced by 2.6 $\times $ . Despite the use of a smaller SCVR, the voltage stacking reduces the supply noise by 3.4 dB and the output voltage drops from 58 to 36 mV. |
| Databáze: | OpenAIRE |
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