Test System for Thin Film Transistor Parameter Extraction in Active Matrix Backplanes
| Autor: | Sanil K Daniel, Sanjiv Sambandan, Aswathi Nair |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
0209 industrial biotechnology
Materials science Transconductance Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology law.invention 020901 industrial engineering & automation law Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Instrumentation Appiled Physics large area electronics Electrical and Electronic Engineering Thin film transistor Liquid-crystal display built-in-self-test business.industry 020208 electrical & electronic engineering Transistor faults testing Electronic Optical and Magnetic Materials Active matrix Capacitor Backplane Thin-film transistor Logic gate Optoelectronics lcsh:Electrical engineering. Electronics. Nuclear engineering business lcsh:TK1-9971 Biotechnology |
| Zdroj: | IEEE Journal of the Electron Devices Society, Vol 7, Pp 638-644 (2019) |
| ISSN: | 2168-6734 |
| DOI: | 10.1109/jeds.2019.2922000 |
| Popis: | Thin film transistor (TFT) active matrix backplanes are used in large area electronic systems, such as displays and image sensors. With backplanes being fabricated on wearable and flexible substrates, the possibilities of operational faults in backplanes have increased. These faults could either be hard faults, such as line opens or shorts or could be softer faults, such as time dependent variations in the TFT transfer characteristics. Real time diagnosis of these faults require built-in-self-test systems. While many such systems have been demonstrated to diagnose hard faults, an easily realizable system to identify soft faults, such as variations in transistor transconductance remain an open challenge. In this paper, we discuss a system that extracts the transconductance by charging and then discharging the pixel capacitor at various gate voltages for an active matrix liquid crystal display backplane. This permits a plot of the time averaged current versus the gate voltage from which the spatial variation of transconductance can be extracted. The details of the design are discussed and a proof of concept with a $3\times 4$ amorphous silicon backplane is demonstrated. |
| Databáze: | OpenAIRE |
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