Effects of Etching Variations on Ge/Si Channel Formation and Device Performance
Autor: | Jiann Lin Chen, Chun Lin Chu, Yiin Kuen Fuh |
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Rok vydání: | 2018 |
Předmět: |
Fabrication
Materials science Dry etching Silicon on insulator Numerical simulation 02 engineering and technology Substrate (electronics) Epitaxy 01 natural sciences Fin (extended surface) Etching (microfabrication) 0103 physical sciences lcsh:TA401-492 General Materials Science 010302 applied physics Nano Express business.industry 021001 nanoscience & nanotechnology Condensed Matter Physics High-defect Ge gate-all-around Optoelectronics lcsh:Materials of engineering and construction. Mechanics of materials 0210 nano-technology business Layer (electronics) |
Zdroj: | Nanoscale Research Letters Nanoscale Research Letters, Vol 13, Iss 1, Pp 1-10 (2018) |
ISSN: | 1556-276X 1931-7573 |
Popis: | During the formation of Ge fin structures on a silicon-on-insulator (SOI) substrate, we found that the dry etching process must be carefully controlled. Otherwise, it may lead to Ge over-etching or the formation of an undesirable Ge fin profile. If the etching process is not well controlled, the top Ge/SOI structure is etched away, and only the Si fin layer remains. In this case, the device exhibits abnormal characteristics. The etching process is emerging as a critical step in device scaling and packaging and affects attempts to increase the packing density and improve device performance. Therefore, it is suggested that optimization of operating the plasma reactor be performed through simulations, in order to not only adjust the process parameters used but also to modify the hardware employed. We are going to develop Ge junction-less devices by employing updated fabrication parameters. Besides, we want to eliminate misfit dislocations at the interface or to reduce threading dislocations by applying cyclic thermal annealing process to meet the goal of obtaining suspended structure of epitaxial Ge layers with high quality. |
Databáze: | OpenAIRE |
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