High data-rate readout logic design of a 512 × 1024 pixel array dedicated for CEPC vertex detector
Autor: | Dong Jianing, W. Lu, Xuejiao Li, Z. Liang, Y. Zhang, Jun Wang, Sebastian Grinstein, Yann Hu, J. Guimaraes da Costa, Xiaomin Wei, Raimon Casanova, Li Long, T. Wu, Luyuan Zhang, Ran Zheng, Wei Wei |
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Přispěvatelé: | Université de Strasbourg (UNISTRA) |
Jazyk: | angličtina |
Rok vydání: | 2019 |
Předmět: |
Physics::Instrumentation and Detectors
vertex detector 01 natural sciences Column (database) 030218 nuclear medicine & medical imaging 03 medical and health sciences 0302 clinical medicine Optics semiconductor detector: pixel 0103 physical sciences [PHYS.PHYS.PHYS-INS-DET]Physics [physics]/Physics [physics]/Instrumentation and Detectors [physics.ins-det] numerical calculations Instrumentation Mathematical Physics detector: design Diode Power density Physics logic Pixel 010308 nuclear & particles physics business.industry Power (physics) CEPC Logic synthesis CMOS electronics: readout business Data compression |
Zdroj: | JINST 21st International Workshop on Radiation Imaging Detectors 21st International Workshop on Radiation Imaging Detectors, Jul 2019, Chania, Greece. pp.C12012, ⟨10.1088/1748-0221/14/12/C12012⟩ |
Popis: | International audience; CMOS Pixel Sensors (CPS) are attractive for CEPC vertex detector construction due to its high granularity, high speed, low material budgets, low power and potential high radiation tolerance. The characteristics of the sensing diode and the readout architecture were studied using several chips with small-scaled pixel array for CEPC vertex detector. This paper will study the design of a high data-rate readout logic design of a 512 × 1024 pixel array. For the innermost layer of CEPC vertex detector, the hit pixel frequency is near 120 MHz, which is several times higher than the design requirements of ALPIDE for ALICE vertex detector. Based on the hit-driven readout scheme in the pixel array of ALPIDE and FEI3, we propose a new peripheral readout logic design. All the double columns of pixels are read out in parallel and a fast readout architecrue of 512 double columns is realized. Meanwhile, a real-time data compression and a trigger-mode operation are supported to reduce the data output. The simulation results indicate the pixel hit frequency in average of 120 MHz can be processed with readout time of 50 ns per pixel and of less than 500 ns per double column of pixels. The layout area is 25.68 × 1.13 mm2. The power density in trigger mode and in triggerless mode are estimated as 25 ∼ 30 mW/cm2 and 35 ∼ 45 mW/cm2 respectively. |
Databáze: | OpenAIRE |
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