Low leakage power gating technique for subnanometer CMOS circuits
| Autor: | Govindaraj Thangavel, Kavitha Manickam |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Materials science
Power gating General Computer Science business.industry Electrical engineering Low leakage Hardware_PERFORMANCEANDRELIABILITY Leakage power Leakage power power gating sleep mode drowsy mode charge recycling CMOS Low-power electronics Hardware_INTEGRATEDCIRCUITS Electrical and Electronic Engineering business Sleep mode Hardware_LOGICDESIGN Electronic circuit |
| Zdroj: | Volume: 24, Issue: 6 5011-5024 Turkish Journal of Electrical Engineering and Computer Science |
| ISSN: | 1303-6203 1300-0632 |
| DOI: | 10.3906/elk-1410-175 |
| Popis: | Static power has become the most important factor in the fabrication of integrated circuits. Power gating techniques minimize leakage currents and help to develop ultra-low-power and high-performance digital circuits. In this paper, a power gating approach is proposed to minimize leakage for subnanometer technologies. Simulation results reveal that the proposed technique reduces maximum of 96% leakage power, 33% dynamic power, 49% drowsy power, and 16{\%} energy as compared to conventional techniques. The proposed technique offers good leakage reduction, even under variation of different operating parameters. |
| Databáze: | OpenAIRE |
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