Efficiency based design flow for fully-integrated class C RF power amplifiers in nanometric CMOS
| Autor: | Fernando Silveira, Rafaella Fiorelli, Nicolas Barabino |
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| Rok vydání: | 2010 |
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| Zdroj: | Digital.CSIC. Repositorio Institucional del CSIC instname ISCAS |
| ISSN: | 0400-2008 |
| Popis: | Trabajo presentado al ISCAS celebrado en Paris del 30 de mayo al 2 de junio de 2010. In this work a design flow for class C radiofrequency (RF) power amplifiers (PA) with on-chip output networks in nanometric technologies is presented. This is a new parasitic-aware method intended to reduce time-consuming iterations which are normally required in fully-integrated designs. Unlike other methods it is based on actual transistors DC characteristics and inductors data both extracted by simulation. Starting from the output power specifications a design space map is generated showing the trade-offs between efficiency and components sizing, thus enabling the selection of the most appropriate design that satisfies the harmonic distortion requirements. As a proof of concept of the proposed method, a design example for an IEEE 802.15.4 2.4 GHz PA in a 90 nm CMOS technology is presented. The authors would like to thank the support of grant ANII BE POS 1250, Uruguayan projects PDT 69/08 and FCE 2007 501; and Catrene European project 2A105SR2 and Avanza I+D Spanish project TSI-020400-2008-71. |
| Databáze: | OpenAIRE |
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