Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks
| Autor: | Aleksa Damljanovic, Giovanni Squillero, Artur Jutman, Anton Tsertov |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2019 |
| Předmět: |
Service (systems architecture)
Computer science media_common.quotation_subject 0211 other engineering and technologies 02 engineering and technology Post-silicon validation Pattern generation 020202 computer hardware & architecture Computer engineering Path length Debugging Path (graph theory) 0202 electrical engineering electronic engineering information engineering Calibration 021106 design practice & management media_common |
| Zdroj: | Proc. IEEE European Test Symposium 2019 (in press) ETS |
| DOI: | 10.5281/zenodo.3362602 |
| Popis: | The increasing number of embedded instruments used to perform test, monitoring, calibration and debug within a semiconductor device has called for a brand new standard—the IEEE 1687. Such a standard resorts to a reconfigurable scan network to provide efficient and flexible access to instruments and to handle complex structures. As it has to deliver reliable service, many approaches, both formal and simulation-based, have been proposed in the literature to perform test, diagnosis and verification of such networks. This paper focuses on the problem of post-silicon validation of a network, a problem that has not been adequately addressed, yet. We analyze the mismatches between the specification and its silicon implementation, and we propose a methodology to detect a subset of them by applying functional patterns and observing the length of the active scan path. Experimental results on ITC2016 benchmarks demonstrate that the proposed approach is broadly applicable, and able to generate very effective sequences. We also classify mismatches that cannot be targeted relying exclusively on the active scan path length information. |
| Databáze: | OpenAIRE |
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