Multi-channel time-tagging module for fast-timing Resistive Plate Chamber detectors
| Autor: | Imad Baptiste Laktineh, L. Mirabito, G-n Lu, C. Combaret, X. Lin-Ma, Xiushan Chen, C. Girerd, C. Guerin |
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| Přispěvatelé: | Institut de Physique des 2 Infinis de Lyon (IP2I Lyon), Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Université de Lyon-Centre National de la Recherche Scientifique (CNRS), Institut des Nanotechnologies de Lyon (INL), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-École supérieure de Chimie Physique Electronique de Lyon (CPE)-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Institut National des Sciences Appliquées (INSA)-Université de Lyon-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS) |
| Jazyk: | angličtina |
| Rok vydání: | 2019 |
| Předmět: |
Data processing
noise logic business.industry Computer science Detector time-to-digital converter resistive plate chamber Signal Line (electrical engineering) efficiency electronics: readout Timestamp [PHYS.PHYS.PHYS-INS-DET]Physics [physics]/Physics [physics]/Instrumentation and Detectors [physics.ins-det] business Field-programmable gate array time resolution AND gate Computer hardware FPGA Communication channel electronics: design |
| Zdroj: | PoS Topical Workshop on Electronics for Particle Physics Topical Workshop on Electronics for Particle Physics, Sep 2019, Santiago de Compostela, Spain. pp.093, ⟨10.22323/1.370.0093⟩ |
| DOI: | 10.22323/1.370.0093⟩ |
| Popis: | International audience; A multi-channel time-tagging module is proposed for fast timing resistive plate chamber (RPC) detectors. It has been designed and implemented in a low-end and low-power cyclone V FPGA. Each channel mainly consists of a time-to-digital converter (TDC) in tapped-delay-line (TDL) architecture. The TDC has three main building blocks: tapped delay line (with registers and a AND logic), fine timestamp converter, and coarse timestamp generator. Several data processing techniques, including prior signal reshaping and noise-immune processing, have been adopted to minimize noise effects. The module has successfully been tested in all-channel simultaneous operation conditions, with 11 ps to 20 ps time resolution and full event-detecting efficiency for all the channels. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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