A solution for automatic parallelization of sequential assembly code
| Autor: | Miroslav Popovic, Vladimir Marinkovic, Djordje Kovacevic, Mladen Stanojevic |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2013 |
| Předmět: |
Speedup
Source code Dead code Computer Networks and Communications Computer science media_common.quotation_subject Data flow graph Energy Engineering and Power Technology Parallel computing assembler computer.software_genre linear scan register allocation SSA form Electrical and Electronic Engineering Redundant code compiler MIPS media_common computer.programming_language Assembly language Mechanical Engineering parser Automatic parallelization Hardware and Architecture Control and Systems Engineering METIS Compiler Unreachable code lcsh:Electrical engineering. Electronics. Nuclear engineering computer lcsh:TK1-9971 |
| Zdroj: | Serbian Journal of Electrical Engineering, Vol 10, Iss 1, Pp 91-101 (2013) |
| ISSN: | 2217-7183 1451-4869 |
| Popis: | Since modern multicore processors can execute existing sequential programs only on a single core, there is a strong need for automatic parallelization of program code. Relying on existing algorithms, this paper describes one new software solution tool for parallelization of sequential assembly code. The main goal of this paper is to develop the parallelizator which reads sequential assembler code and at the output provides parallelized code for MIPS processor with multiple cores. The idea is the following: the parser translates assembler input file to program objects suitable for further processing. After that the static single assignment is done. Based on the data flow graph, the parallelization algorithm separates instructions on different cores. Once sequential code is parallelized by the parallelization algorithm, registers are allocated with the algorithm for linear allocation, and the result at the end of the program is distributed assembler code on each of the cores. In the paper we evaluate the speedup of the matrix multiplication example, which was processed by the parallelizator of assembly code. The result is almost linear speedup of code execution, which increases with the number of cores. The speed up on the two cores is 1.99, while on 16 cores the speed up is 13.88. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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