Circuit-level evaluation of a new zero-cost transistor in a embedded non-volatile memory CMOS technology
| Autor: | Arnaud Regnier, Stephan Niel, Alexandre Malherbe, Abderrezak Marzaki, Sebastien Haendler, Hassen Aziza, Franck Julien, Thomas Sardin, M. Mantelli, Philippe Lorenzini, Paul Devoge |
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| Přispěvatelé: | Institut des Matériaux, de Microélectronique et des Nanosciences de Provence (IM2NP), Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS)-Aix Marseille Université (AMU), Electronique pour Objets Connectés (EpOC), Université Côte d'Azur (UCA)-Polytech Nice-Sophia-Université Nice Sophia Antipolis (... - 2019) (UNS), COMUE Université Côte d'Azur (2015-2019) (COMUE UCA)-COMUE Université Côte d'Azur (2015-2019) (COMUE UCA), STMicroelectronics [Rousset] (ST-ROUSSET), STMicroelectronics, Aix Marseille Université (AMU)-Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS), Université Nice Sophia Antipolis (1965 - 2019) (UNS), COMUE Université Côte d'Azur (2015-2019) (COMUE UCA)-COMUE Université Côte d'Azur (2015-2019) (COMUE UCA)-Polytech Nice-Sophia-Université Côte d'Azur (UCA) |
| Jazyk: | angličtina |
| Rok vydání: | 2021 |
| Předmět: |
analog
Computer science Transistor Spice CMOS Semiconductor device modeling zero-cost Integrated circuit Ring oscillator Hardware_PERFORMANCEANDRELIABILITY law.invention Non-volatile memory MOSFET law Hardware_GENERAL middle-voltage circuit simulation Electronic engineering Hardware_INTEGRATEDCIRCUITS transistor ring oscillator [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Electronic circuit Hardware_LOGICDESIGN |
| Zdroj: | 2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) 2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Jun 2021, Montpellier, France. pp.1-5, ⟨10.1109/DTIS53253.2021.9505137⟩ DTIS |
| DOI: | 10.1109/DTIS53253.2021.9505137⟩ |
| Popis: | International audience; This work presents a new transistor architecture developed by reusing already existing fabrication process steps in an embedded non-volatile memory (eNVM) CMOS technology. The proposed transistor is derived from an existing high-voltage transistor and is free in terms of photomasks and process steps, making it ideal for low-cost products. The new transistor is fabricated then electrically characterized, showing good analog performances. A SPICE (Simulation Program with Integrated Circuit Emphasis) model of the new device is developed to assess its circuit-level performances through electrical circuit simulation. The in-circuit performances of the new device are evaluated based on different ring oscillator circuits. A comparison with the existing high-voltage transistor is carried out considering performance parameters such as the oscillating frequency to demonstrate the appeal of our new transistor. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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