Interpreting SSTA Results with Correlation
| Autor: | Philippe Maurine, Nadine Azemard, Zeqin Wu, Gille Ducharme |
|---|---|
| Přispěvatelé: | Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Conception et Test de Systèmes MICroélectroniques (SysMIC), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Département de Mathématiques [Montpellier], Université Montpellier 2 - Sciences et Techniques (UM2), Springer |
| Jazyk: | angličtina |
| Rok vydání: | 2009 |
| Předmět: |
010302 applied physics
Delay calculation Statistical static timing analysis Conditional Moment Circuit design Worst-case Timing Analysis (WTA) Static timing analysis Topology (electrical circuits) 02 engineering and technology Gate-to-gate Delay Correlation (GDC) 01 natural sciences Standard deviation 020202 computer hardware & architecture Correlation 0103 physical sciences Path (graph theory) Statistics 0202 electrical engineering electronic engineering information engineering Statis- tical Static Timing Analysis (SSTA) Statis-tical Static Timing Analysis (SSTA) [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Mathematics Hardware_LOGICDESIGN |
| Zdroj: | 19th International Workshop on Power and Timing Modeling Optimization and Simulation PATMOS: Power And Timing Modeling, Optimization and Simulation PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.16-25, ⟨10.1007/978-3-642-11802-9_6⟩ Lecture Notes in Computer Science ISBN: 9783642118012 PATMOS |
| DOI: | 10.1007/978-3-642-11802-9_6⟩ |
| Popis: | International audience; Statistical Static Timing Analysis (SSTA) is becoming necessary; but has not been widely adopted. One of those arguments against the use is that results of SSTA are difficult to make use of for circuit design. In this paper, by introducing conditional moments, we propose a path-based statistical timing approach, which permits us to consider gate topology and switching process in-duced correlations. With the help of this gate-to-gate delay correlation, differ-ences between results of SSTA and those of Worst-case Timing Analysis (WTA) are interpreted. Numerical results demonstrate that path delay means and standard deviations estimated by the proposed approach have absolute val-ues of relative errors respectively less than 5% and 10%. |
| Databáze: | OpenAIRE |
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