A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification
| Autor: | Edwin Rijpkema, Andrei Radulescu, Om P. Gangwal, Kees Goossens, Santiago González Pestana, John Dielissen |
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| Přispěvatelé: | Publishing Association, EDA, EDAA - European design and Automation Association |
| Jazyk: | angličtina |
| Rok vydání: | 2005 |
| Předmět: |
[INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR]
business.industry Computer science Design flow Software performance testing Application software computer.software_genre [SPI.TRON] Engineering Sciences [physics]/Electronics Software Network on a chip Computer architecture SystemC Embedded system VHDL Hardware_INTEGRATEDCIRCUITS System on a chip business computer computer.programming_language |
| Zdroj: | DATE |
| Popis: | Systems on chip (SOC) are composed of intellectual property blocks (IP) and interconnect. While mature tooling exists to design the former, tooling for interconnect design is still a research area. In this paper we describe an operational design flow that generates and configures application-specific network on chip (NOC) instances, given application communication requirements. The NOC can be simulated in SystemC and RTL VHDL. An independent performance verification tool verifies analytically that the NOC instance (hardware) and its configuration (software) together meet the application performance requirements. The AEthereal NOC's guaranteed performance is essential to replace time-consuming simulation by fast analytical performance validation. As a result, application-specific NOCs that are guaranteed to meet the application's communication requirements are generated and verified in minutes, reducing the number of design iterations. A realistic MPEG SOC example substantiates our claims. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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