Scalable FPGA graph model to detect routing faults
| Autor: | Carmelo Loiacono, Francesco Savarese, Boyang Du, S.F. Finocchiaro, Luca Sterpone, Gianpiero Cabodi |
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| Rok vydání: | 2016 |
| Předmět: |
Integrated circuit interconnections
Computer science Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Fault (power engineering) Computer Science::Hardware Architecture 0202 electrical engineering electronic engineering information engineering Static random-access memory Field-programmable gate array Routing Measurement business.industry Circuit faults Field programmable gate arrays Computational modeling 020202 computer hardware & architecture Soft error Computer engineering Integrated circuit modeling Embedded system Scalability Netlist Routing (electronic design automation) Fault model business Field programmable gate arrays Circuit faults Routing Integrated circuit modeling Computational modeling Integrated circuit interconnections Measurement |
| Zdroj: | IOLTS |
| DOI: | 10.1109/iolts.2016.7604690 |
| Popis: | The SRAM cells that form the configuration memory of an SRAM-based FPGA make such FPGAs particularly vulnerable to soft errors. A soft error occurs when ionizing radiation corrupts the data stored in a circuit. The error persists until new data is written. Soft errors have long been recognized as a potential problem as radiation can come from a variety of sources. This paper presents an FPGA fault model focusing on routing aspects. A graph model of SRAM nodes behavior in case of fault, starting from netlist description of well known FPGA models, is presented. It is also performed a classification of possible logical effects of a soft error in the configuration bit controlling, providing statistics on the possible numbers of faults. Finally it is reported the definition of fault metrics computed on a set of complex benchmarks proving the effectiveness of our approach. |
| Databáze: | OpenAIRE |
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