TRIG
| Autor: | Rebecca Park, Bert Moons, Jake Hillard, Daniel Bankman, Gage Hills, Lita Yang, Max M. Shulaker, Boris Murmann, Marian Verhelst, Alex Kahng, Subhasish Mitra, H.-S. Philip Wong |
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| Rok vydání: | 2018 |
| Předmět: |
Digital electronics
Very-large-scale integration business.industry Computer science Circuit design 020208 electrical & electronic engineering Transistor Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Carbon nanotube 020202 computer hardware & architecture law.invention Semiconductor law Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Hardware acceleration business Hardware_LOGICDESIGN Electronic circuit Efficient energy use |
| Zdroj: | DAC |
| DOI: | 10.1145/3195970.3196132 |
| Popis: | The energy efficiency demands of future abundant-data applications, e.g., those which use inference-based techniques to classify large amounts of data, exceed the capabilities of digital systems today. Field-effect transistors (FETs) built using nanotechnologies, such as carbon nanotubes (CNTs), can improve energy efficiency significantly. However, carbon nanotube FETs (CNFETs) are subject to process variations inherent to CNTs: variations in CNT type (semiconductor or metallic), CNT density, or CNT diameter, to name a few. These CNT variations can degrade CNFET benefits at advanced technology nodes. One path to overcome CNT variations is to co-optimize CNT processing and CNFET circuit design; however, the required CNT process advancements have not been achieved experimentally. We present a new design approach (TRIG, Technique for Reducing errors using Iterative Gray code) to overcome process variations in hardware accelerators targeting inference-based applications that use serial matrix operations (serial: accumulated over at least 2 clock cycles). We demonstrate that TRIG can retain the major energy efficiency benefits (quantified using Energy Delay Product or EDP) of CNFETs despite CNT variations that exist in today's CNFET fabrication - without requiring further CNT processing improvements to overcome CNT variations. As a case study, we analyze the effectiveness of TRIG for a binary neural network hardware accelerator that classifies images. Despite CNT variations that exist today, TRIG can maintain 99% (90%) of projected EDP benefits of CNFET digital circuits for 90% (99%) image classification accuracy target. We also demonstrate experimentally fabricated CNFET circuits to compute scalar product (a common matrix operation, also called dot product), with and without TRIG: TRIG reduces the mean difference between the expected result (no errors) and the experimentally computed result by 30 × in the presence of CNT variations, shown experimentally. |
| Databáze: | OpenAIRE |
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