An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch
| Autor: | Alexander Petrie, Eric Swindlehurst, Yen-Cheng Kuan, Hunter Jensen, Mau-Chung Frank Chang, Jieh-Tsorng Wu, Yixin Song, Shiuh-hua Wood Chiang |
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| Rok vydání: | 2019 |
| Předmět: |
Physics
Spurious-free dynamic range 020208 electrical & electronic engineering 8-bit Successive approximation ADC Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Capacitance 020202 computer hardware & architecture law.invention Capacitor Parasitic capacitance CMOS Sampling (signal processing) law Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Electrical and Electronic Engineering |
| Zdroj: | ESSCIRC |
| Popis: | An 8-bit 10-GHz $8\times $ time-interleaved SAR ADC in 28-nm CMOS incorporates an aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A dual-path bootstrapped switch decouples critical signal from nonlinear capacitance to boost the sampling SFDR by more than 5 dB. The ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW, yielding an FoM of 37 fJ/conv.-step, the lowest among the reported ADCs with similar speeds and resolutions and more than $2\times $ improvement from the state-of-the-art. |
| Databáze: | OpenAIRE |
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