SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6–3.6-μW/DMIPS 40–80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode
| Autor: | Charlotte Frenkel, Denis Flandre, Roghayeh Saeidi, Thomas Haine, David Bol, Remi Dekimpe, Ludovic Moreau, Pengcheng Xu, Maxime Schramme |
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| Přispěvatelé: | UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique, University of Zurich, Bol, David |
| Jazyk: | angličtina |
| Rok vydání: | 2021 |
| Předmět: |
Physics
Power management business.industry 2208 Electrical and Electronic Engineering Transistor Electrical engineering Silicon on insulator Voltage regulator Hardware_PERFORMANCEANDRELIABILITY AC power law.invention Microcontroller law Hardware_INTEGRATEDCIRCUITS 570 Life sciences biology Static random-access memory Electrical and Electronic Engineering business Energy (signal processing) Voltage 10194 Institute of Neuroinformatics |
| Zdroj: | IEEE Journal of Solid State Circuits, Vol. 56, no.7, p. 2256-2269 (2021) |
| Popis: | Preventing device obsolescence in Internet-ofthings (IoT) is mandatory for its massive deployment to be ecologically sustainable. This calls for ultralow-power (ULP) reprogrammable microcontroller units (MCUs) for long lifetime, yet with sufficient computing performance to extract the meaningful information from the sensed data before transmitting it to the cloud. In this article, we present the SleepRunner MCU with logic/memory/power management co-optimization for best exploitation of the forward back biasing (FBB) capability in fully-depleted silicon-on-insulator (FDSOI) technologies. For low active power, we use ultralow-voltage (ULV) low-Vt logic with upsized gate length and asymmetric FBB, a ULP SRAM macro with low read-access energy and switched-capacitor voltage regulators (SCVRs) for ULV supply generation from a single I/O voltage. The custom ULP SRAM macro is based on an ultralowleakage (ULL) FBB-compatible bitcell for low SRAM retention power. In addition, a dual-loop digital unified frequency/backbias regulation (UFBR) system efficiently compensates process and temperature variations with short wakeup from the zero-back-bias deep-sleep mode. Performance is measured for a synthetic benchmark and biomedical inference applications. The measured 40-MHz 2.6-μW/DMIPS (3.3 μW/MHz) active and 131-nW/kB deep-sleep power consumptions with CPU state retention are respectively 3× and 2.5× lower than for a conventional MCU design in this technology. This demonstrates the interest of 28-nm FDSOI with the proposed FBB-driven system optimization for ULP MCUs. Index Terms—Adaptive process, voltage, and temperature (PVT) compensation, CMOS digital integrated circuits, fullydepleted silicon-on-insulator (FDSOI), microcontroller, nearthreshold computing, SRAM, ultralow power (ULP), ultralow voltage (ULV). |
| Databáze: | OpenAIRE |
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