Analysis and Design of Integrated Blocks for a 6.25 GHz Spacefibre PLL
| Autor: | Bruno Neri, Sergio Saponara, Marco Mestice, Gabriele Ciarpi |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2020 |
| Předmět: |
PLL (phase-locked loop)
Computer science TID (total ionization dose) 02 engineering and technology lcsh:Chemical technology 01 natural sciences Biochemistry Article Analytical Chemistry law.invention charge pump Frequency divider Voltage-controlled oscillator law 0103 physical sciences Phase noise 0202 electrical engineering electronic engineering information engineering Electronic engineering Hardware_INTEGRATEDCIRCUITS lcsh:TP1-1185 Electrical and Electronic Engineering frequency divider Instrumentation Electronic circuit 010308 nuclear & particles physics 020208 electrical & electronic engineering Transistor dBc SEE (single event effects) Spacefibre Chip Atomic and Molecular Physics and Optics rad-hard Phase-locked loop Charge pump Phase/frequency detector Rad-hard phase/frequency detector Phase frequency detector |
| Zdroj: | Sensors (Basel, Switzerland) Sensors Volume 20 Issue 14 Sensors, Vol 20, Iss 4013, p 4013 (2020) |
| ISSN: | 1424-8220 |
| Popis: | The design of a Phase-Locked Loop (PLL) to generate the clock reference for the new Spacefibre standard is presented in this paper. Spacefibre has been recently released by the European Space Agency (ESA) and supports up to 6.25 Gbps for on-board satellite communications. Taking as a starting point a rad-hard 6.25 GHz Voltage Controlled Oscillator in 65 nm technology, this work presents the design of the key blocks for an integrated PLL: a Triple Modular Redundancy Phase/Frequency Detector, a Charge Pump, and a passive Loop Filter. The modeling activities carried out in an Advanced Design System have proven that the proposed PLL can be completely integrated on-chip, with a Loop Filter area consumption of only 6000 µ m2 (considering the 65 nm technology). The design of active circuits has been carried out at the transistor level in a Cadence Virtuoso environment, implementing both system and layout rad-hard techniques, and different solutions are discussed in this paper. As a result, a compact (0.09 mm2), low power (10.24 mW), dead zone free and rad-hard PLL is obtained with a Phase Noise below &minus 80 dBc/Hz @ 1 MHz. A preliminary block view and floor plan of the test chip is also proposed. |
| Databáze: | OpenAIRE |
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