Performance-effective operation below Vcc-min
| Autor: | Ladas, N., Sazeides, Yiannakis, Desmet, V. |
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| Rok vydání: | 2010 |
| Předmět: |
Technology and Engineering
Computer science probability Reliability (computer networking) random fault distribution Real-time computing SIMPLE method Hardware_PERFORMANCEANDRELIABILITY Probability theory Circuit miniaturization probability theory block-disabled cache Computer software Cache capacity arrays continuous circuit miniaturization dynamic voltage scaling Cache algorithms Block (data storage) cache storage Performance loss Faulty cells cache techniques fault diagnosis Low voltages Reliability engineering Dynamic voltage scaling Probability distributions probability analysis Key (cryptography) Process Variability Cache Reliability analysis Low voltage |
| Zdroj: | ISPASS 2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2010) ISPASS 2010-IEEE International Symposium on Performance Analysis of Systems and Software 2010 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2010 |
| DOI: | 10.1109/ispass.2010.5452017 |
| Popis: | Continuous circuit miniaturization and increased process variability point to a future with diminishing returns from dynamic voltage scaling. Operation below Vcc-min has been proposed recently as a mean to reverse this trend. The goal of this paper is to minimize the performance loss due to reduced cache capacity when operating below Vcc-min. A simple method is proposed: disable faulty blocks at low voltage. The method is based on observations regarding the distributions of faults in an array according to probability theory. The key lesson, from the probability analysis, is that as the number of uniformly distributed random faulty cells in an array increases the faults increasingly occur in already faulty blocks. The probability analysis is also shown to be useful for obtaining insight about the reliability implications of other cache techniques. For one configuration used in this paper, block disabling is shown to have on the average 6.6% and up to 29% better performance than a previously proposed scheme for low voltage cache operation. Furthermore, block-disabling is simple and less costly to implement and does not degrade performance at or above Vcc-min operation. Finally, it is shown that a victim-cache enables higher and more deterministic performance for a block-disabled cache. ©2010 IEEE. 223 234 Sponsors: IEEE Computer Society NSF Intel Conference code: 80374 Cited By :13 |
| Databáze: | OpenAIRE |
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