Reducing the Delay for Decoding Instructions by Predicting Their Source Register Operands
| Autor: | Gyeong Il Min, Chang Hyun Kim, Sang-Hyun Park, Jaeyung Jun, Seon Wook Kim, Hun Jae Lee |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
decoding
Computer Networks and Communications Computer science Pipeline (computing) lcsh:TK7800-8360 02 engineering and technology Operand Execution time 0202 electrical engineering electronic engineering information engineering Overhead (computing) Electrical and Electronic Engineering Arithmetic register operand detection lcsh:Electronics Process (computing) ComputerSystemsOrganization_PROCESSORARCHITECTURES 020202 computer hardware & architecture ISAs Data dependency Hardware and Architecture Control and Systems Engineering Signal Processing data dependency Hardware_CONTROLSTRUCTURESANDMICROPROGRAMMING Critical path method Decoding methods |
| Zdroj: | Electronics Volume 9 Issue 5 Electronics, Vol 9, Iss 820, p 820 (2020) |
| ISSN: | 2079-9292 |
| DOI: | 10.3390/electronics9050820 |
| Popis: | The fetched instructions would have data dependency with in-flight ones in the pipeline execution of a processor, so the dependency prevents the processor from executing the incoming instructions for guaranteeing the program&rsquo s correctness. The register and memory dependencies are detected in the decode and memory stages, respectively. In a small embedded processor that supports as many ISAsas possible to reduce code size, the instruction decoding to identify register usage with the dependence check generally results in long delay and sometimes a critical path in its implementation. For reducing the delay, this paper proposes two methods&mdash One method assumes the widely used source register operand bit-fields without fully decoding the instructions. However, this assumption would cause additional stalls due to the incorrect prediction thus, it would degrade the performance. To solve this problem, as the other method, we adopt a table-based way to store the dependence history and later use this information for more precisely predicting the dependency. We applied our methods to the commercial EISC embedded processor with the Samsung 65nm process thus, we reduced the critical path delay and increased its maximum operating frequency by 12.5% and achieved an average 11.4% speed-up in the execution time of the EEMBC applications. We also improved the static, dynamic power consumption, and EDP by 7.2%, 8.5%, and 13.6%, respectively, despite the implementation area overhead of 2.5%. |
| Databáze: | OpenAIRE |
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