Study and Comparison of Hardware Methods for Distributing Memory Bank Accesses in Many‐core Architectures
| Autor: | Arthur Vianes, Frederic Rousseau |
|---|---|
| Přispěvatelé: | Kalray, System Level Synthesis (SLS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), BEN TITO, Laurence |
| Rok vydání: | 2021 |
| Předmět: |
010302 applied physics
Hardware_MEMORYSTRUCTURES interconnect Computer science business.industry [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics index schemes 02 engineering and technology 01 natural sciences 020202 computer hardware & architecture PACS 8542 Memory bank Many core local memory Embedded system 0103 physical sciences 0202 electrical engineering electronic engineering information engineering [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Networks on chip business many-core |
| Zdroj: | Multi-Processor System-on-Chip 1 Multi-Processor System-on-Chip 1: Architectures Multi-Processor System-on-Chip 1: Architectures, wiley, chichester, uk, pp.161-194, 2021, 978-1-789-45021-7 |
| Popis: | International audience; Multi-core and many-core architectures have evolved towards a set of clusters, each cluster being composed of a set of cores communicating with each other through Network-on-Chip. Each cluster integrates cache memory and a local memory shared by all the cores of the cluster. Local memory bandwidth should be able to support all the accesses requested by the cores to get the maximum performance. One solution to reach this objective is to split the local memory in several banks, accessible in parallel. If some cores get access at the same bank simultaneously, this leads to memory bank conflict. A conflict increases the latency for the other cores, decreasing the overall bandwidth.In this work, we start to present in detail when collisions happen and their consequences on the running application. We focus then on hardware solutions to improve the performances of multi-bank accesses, going from hash-function address coding to additional memory banks. All these solutions have been simulated on the MPPA Kalray processor and we provide a comparison and discussions about obtained results, mainly to highlight that there is no universal solution ! |
| Databáze: | OpenAIRE |
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