Analog/RF test ordering in the early stages of production testing
Autor: | Salvador Mir, Emmanuel Simeu, N. Akkouche, Mustapha Slamani |
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Přispěvatelé: | Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), Wireless Test Development Group, IBM, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA) |
Rok vydání: | 2012 |
Předmět: |
0209 industrial biotechnology
Engineering business.industry Virtual circuit Statistical model 02 engineering and technology Fault (power engineering) Integrated Circuits 020202 computer hardware & architecture Set (abstract data type) 020901 industrial engineering & automation CMOS analogue-circuit-testing PACS 85.42 0202 electrical engineering electronic engineering information engineering Electronic engineering Device under test CMOS-integrated-circuits Radio frequency [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics business Electronic circuit |
Zdroj: | VTS Proc. of 30th IEEE VLSI Test Symposium 30th IEEE VLSI Test Symposium 30th IEEE VLSI Test Symposium, Apr 2012, Hawaii, United States. pp.25-30, ⟨10.1109/VTS.2012.6231075⟩ |
DOI: | 10.1109/vts.2012.6231075 |
Popis: | ISBN 978-1-4673-1073-4; International audience; Ordering of analog/RF tests is important for the identification of redundant tests. Most methods for test ordering are based on a representative set of defective devices. However, at the beginning of production testing, there is little or no data on defective devices. Obtaining this data through defect and fault simulation is unrealistic for most advanced analog/RF devices. In this work, we will present a method for analog/RF test ordering that uses only data from a small set of functional circuits. A statistical model of the device under test is constructed from this data. This model is next used for sampling a large number of virtual circuits which will also include defective ones. These virtual defective circuits are then used for ordering analog/RF tests using feature selection techniques. Experimental results for an IBM RF front-end have demonstrated the validity of this technique for test grading and compaction. |
Databáze: | OpenAIRE |
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