A fast and accurate methodology for power estimation and reduction of programmable architectures
| Autor: | Erwan Piriou, Raphael David, Fahim Rahim, Solaiman Rahim |
|---|---|
| Přispěvatelé: | Département d'Architectures, Conception et Logiciels Embarqués-LIST (DACLE-LIST), Laboratoire d'Intégration des Systèmes et des Technologies (LIST), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Atrenta Inc., Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)) |
| Jazyk: | angličtina |
| Rok vydání: | 2013 |
| Předmět: |
010302 applied physics
RISC processors Power estimations Programmable architectures Register transfer level 02 engineering and technology 01 natural sciences 020202 computer hardware & architecture Instruction-level Power Optimization [SPI]Engineering Sciences [physics] 0103 physical sciences 0202 electrical engineering electronic engineering information engineering [INFO]Computer Science [cs] Design space exploration Register files |
| Zdroj: | 16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013 16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013;, Mar 2013, Grenoble, France. pp.1054-1055, ⟨10.7873/DATE.2013.220⟩ |
| DOI: | 10.7873/DATE.2013.220⟩ |
| Popis: | Conference of 16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013 ; Conference Date: 18 March 2013 Through 22 March 2013; Conference Code:100164; International audience; We present a power optimization methodology that provides a fast and accurate power model for programmable architectures. The approach is based on a new tool that estimates power consumption from a register transfer level (RTL) module description, activity files and technology library. It efficiently provides an instruction-level accurate power model and allows design space exploration for the register file. We demonstrate a 19% improvement for a standard RISC processor. |
| Databáze: | OpenAIRE |
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