A Distributed Voltage Controlled Oscillator in a standard 65nm CMOS Process

Autor: Jean-Baptiste Begueret, Hervé Lapuyade, E. Chataigner, N. Seller
Přispěvatelé: Laboratoire de l'intégration, du matériau au système (IMS), Université Sciences et Technologies - Bordeaux 1-Institut Polytechnique de Bordeaux-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics [Crolles] (ST-CROLLES), Lapuyade, Hervé
Rok vydání: 2006
Předmět:
Offset (computer science)
Materials science
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Hardware_PERFORMANCEANDRELIABILITY
02 engineering and technology
7. Clean energy
Computer Science::Hardware Architecture
Voltage-controlled oscillator
Computer Science::Emerging Technologies
Hardware_GENERAL
Low-power electronics
Phase noise
Hardware_INTEGRATEDCIRCUITS
0202 electrical engineering
electronic engineering
information engineering

Electronic engineering
[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
business.industry
020208 electrical & electronic engineering
Electrical engineering
020206 networking & telecommunications
Condensed Matter::Mesoscopic Systems and Quantum Hall Effect
Computer Science::Other
Vackář oscillator
CMOS
Power consumption
Distributed Voltage Controlled Oscillator
Cmos process
business
Zdroj: Proceedings of the 2006 Ph.D Research in Microelectronics and Electronics conference (PRIME 2006)
2006 Ph.D Research in Microelectronics and Electronics conference (PRIME 2006)
2006 Ph.D Research in Microelectronics and Electronics conference (PRIME 2006), Jun 2006, France. pp.93-96
DOI: 10.1109/rme.2006.1689904
Popis: This paper presents the design of a distributed voltage controlled oscillator (DVCO). This oscillator has been designed in a low-cost low-power standard STMicroelectronics 65nm CMOS process. The DVCO achieves a tuning range from 9.6GHz to 11.6GHz, a phase noise better than -l0ldBc/Hz at lMHz offset from the carrier and a total power consumption of 29mW.
Databáze: OpenAIRE