Mitigating read & write errors in STT-MRAM memories under DVS
| Autor: | Rosa Rodriguez-Montanes, Elena Ioana Vatajelu, Joan Figueras, Michel Renovell |
|---|---|
| Přispěvatelé: | Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Universitat Politècnica de Catalunya [Barcelona] (UPC), TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS) |
| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Memory failure Magnetoresistive random-access memory Hardware_MEMORYSTRUCTURES Computer science business.industry Voltage control 01 natural sciences Reliability (semiconductor) PACS 85.42 Embedded system 0103 physical sciences [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics business Voltage |
| Zdroj: | ETS 22nd IEEE European Test Symposium ETS: European Test Symposium ETS: European Test Symposium, May 2017, Limassol, Cyprus. ⟨10.1109/ETS.2017.7968209⟩ |
| DOI: | 10.1109/ets.2017.7968209 |
| Popis: | International audience; In this paper we propose a methodology for reliability evaluation, failure prediction, and failure mitigation of a STT-MRAM memory under different supply voltage conditions (i.e., DVS scenarios). The methodology is based on the design of read/write failure predictor registers which are able to predict the memory failure probability for a given DVS scenario. The predicted results are used to re-tune the supply voltage such that the memory reliability is assured. |
| Databáze: | OpenAIRE |
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