Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA

Autor: Nguyen My Qui, Chang Hong Lin, Poki Chen
Rok vydání: 2020
Předmět:
Instructions per cycle
General Computer Science
Computer science
field-programmable gate arrays (FPGA)
0211 other engineering and technologies
02 engineering and technology
computer.software_genre
dynamic scheduling
law.invention
Instruction set
law
0202 electrical engineering
electronic engineering
information engineering
General Materials Science
Field-programmable gate array
021106 design practice & management
256-bit
Fetch
General Engineering
RISC-V
ComputerSystemsOrganization_PROCESSORARCHITECTURES
Microprocessor
Computer architecture
Very long instruction word
microprocessor
020201 artificial intelligence & image processing
lcsh:Electrical engineering. Electronics. Nuclear engineering
Compiler
Hardware_CONTROLSTRUCTURESANDMICROPROGRAMMING
lcsh:TK1-9971
computer
Very long instruction word (VLIW)
Zdroj: IEEE Access, Vol 8, Pp 172996-173007 (2020)
ISSN: 2169-3536
DOI: 10.1109/access.2020.3024851
Popis: This study describes the design and implementation of a 256-bit very long instruction word (VLIW) microprocessor based on the new RISC-V instruction set architecture (ISA). Base integer RV32I and extension instruction sets, including RV32M, RV32F, and RV32D, are selected to implement our VLIW hardware. The proposed architecture packs up eight 32-bit instruction flows, each of which performs fixed operational functions to create a 256-bit long instruction format. However, one obstacle of studying new ISAs, similar to RISC-V, to design VLIW microprocessors is the lack of dedicated compilers. Developing an architecture-specific compiler is really challenging. An instruction scheduler is integrated to dynamically schedule independent instructions into the VLIW instruction format. This scheduler is used to overcome the lack of a dedicated RISC-V VLIW compiler and leverage the available RISC-V GNU toolchain. Unlike conventional VLIWs, our proposed architecture is organized into six main stages, namely, fetch, instruction scheduler, decode, execute, data memory, and writeback. The complete design is verified, synthesized, and implemented on a Xilinx Virtex-6 (xc6vlx240t-1-ff1156). Maximum synthesis frequency reaches 83.739 MHz. The proposed RISC-V-based VLIW architecture obtains an average instructions per cycle value that outperforms that of existing open-source RISC-V cores.
Databáze: OpenAIRE
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